1. Field of the Invention
The present invention relates to an apparatus for testing an integrated circuit or a large scale integrated circuit, hereinafter referred to as an LSI tester, and more particularly, to an apparatus which applies predetermined input test data to an integrated circuit to be tested, hereinafter referred to as a D.U.T., i.e., Device Under Test, and compares a signal output from the D.U.T. in response to the input test data with a predetermined expected output test data, to determine whether the D.U.T. is functional or non-functional.
2. Description of the Related Art
A known typical LSI tester includes a buffer memory, in which input data for testing a D.U.T., corresponding expected output data, and timing changing bits for defining an application mode of the input data are stored. This apparatus is constituted in such a manner that a test of the D.U.T. is made in accordance with the timing changing bits preset with respect to each of addresses in the buffer memory. Namely, the application mode of the test pattern is fixedly defined based on the order in which the test pattern to be employed is stored in the buffer memory. Therefore, to change the application mode of the test pattern, the writing into the buffer memory must be inevitably changed, and further, to realize a variety of application modes, the capacity of the buffer memory must be increased.
Accordingly, the LSI tester of the prior art has disadvantages in that; first, it is impossible to freely change the application mode of the test pattern when the test is carried out with an arbitrary test pattern; second, since a change in writing into the buffer memory is necessary, the test cannot be efficiently carried out.